In a pipeline analog-to-digital converter, a level conversion circuit is usually used to implement conversion between a high level signal and a low level signal. With an increasingly high requirement for a speed indicator of the pipeline analog-to-digital converter, improving a speed of the level conversion circuit becomes one means of improving a speed of the pipeline analog-to-digital converter.
As shown in FIG. 1, a level conversion circuit used in the prior art includes a PMOS (P-type metal-oxide-semiconductor) transistor T1, a PMOS transistor T2, an NMOS (N-type metal-oxide-semiconductor) transistor T3, an NMOS transistor T4, and a phase inverter, where both a source of T1 and a source of T2 are connected to a power supply positive electrode AVDD, a drain of T1 is connected to a gate of T2, a gate of T1 is connected to a drain of T2, a gate of T3 is connected to an output end clk of a square wave generation circuit, a source of T3 is connected to a source of T4 and is grounded, a drain of T3 is connected to the drain of T1, a gate of T4 is connected to the gate of T3 by using the phase inverter, and a drain of T4 is connected to the drain of T2 and is used as an output end clkout of the level conversion circuit for connecting to a load. A specific working principle is as follows: It is assumed that a value of AVDD is 2 V, a lowest voltage value of a signal output by the square wave generation circuit is 0 V, and a highest voltage value is 1 V. When clk=0 V, a gate voltage of T3 is 0 V, and T3 is cut off, whereas a gate voltage of T4 is converted into 1 V by using the phase inverter and therefore T4 is conducted. In this case, clkout=0 V. In this case, T1 is conducted because a gate voltage of T1 is less than a source voltage of T1; T2 is cut off because a gate voltage of T2 is AVDD=2 V. When clk=1 V, T3 is conducted because the gate voltage of T3 is greater than a source voltage of T3, and T4 is cut off. A drain voltage of T3 and the gate voltage of T2 are 0. T2 is conducted because the gate voltage of T2 is less than a source voltage of T2. In this case, clkout=AVDD=2 V, and T1 is cut off. In this way, level signal conversion is completed.
However, in the foregoing implementation process, when clk changes from zero to a highest voltage, states of T1, T2, and T3 change in the following sequence: first T3 is conducted, then T2 can be conducted, and finally T1 changes from a conducted state to a cut-off state. That is, in a process in which T3 changes from a cut-off state to a conducted state, a status in which both T3 and T1 are conducted exists. Therefore, the drain voltage of T3 cannot immediately change to 0 V but instead, gradually changes from an intermediate value of AVDD to 0 V. As a result, a conducting speed of T2 slows down, and further a speed at which clkout changes from 0 to AVDD becomes slow. That is, a conversion speed of the level conversion circuit is decreased.